1. Field of the Invention
The present invention relates in general to the field of computers and similar technologies, and in particular to software utilized in this field. Still more particularly, it relates to an improved method and system for managing transient instruction streams.
2. Description of the Related Art
Using a cache to bridge the performance gap between a processor and main memory has become important in data processing systems, from personal computers, to work stations, to data processing systems with high performance processors. A cache memory is an auxiliary memory that provides a buffering capability through which a relatively slow main memory can interface with a processor at the processor's cycle time to optimize the performance of the data processing system. Requests are first sent to the cache to determine whether the data or instructions requested are present in the cache memory. A ‘hit’ occurs when the desired information is found in the cache. A ‘miss’ occurs when a request or access to the cache does not produce the desired information. In response to a miss, one of the cache ‘lines’ is replaced with a new one.
In some current software applications, the instruction footprint is large and certain instruction streams, known as transient streams, are executed infrequently. As a result, the number of processor cycles between accessing instructions in a cache line can become very large. These cache lines of instructions are typically stored in a cache hierarchy of a computer system, and are often duplicated in inclusive Level 1 (L1), Level 2 (L2), and Level 3 (L3) caches. However, these infrequently-used instructions pollute the caches. That is, they cause other, more useful data to be cast out from the cache. Likewise, they take up space in the cache until they are aged out as new data comes in. In a multi-cache hierarchy, several copies of a given cache line may pollute multiple caches. In view of the foregoing, there is a need to manage which instruction streams make use of lower-level caches and which do not, in order to increase the availability of more useful non-transient instructions and data.